The Central Processing Unit and the Fetch-Decode-Execute Cycle
The central processing unit (CPU) executes machine-code instructions through a repeating fetch-decode-execute cycle.
Summary
The central processing unit (CPU) executes machine-code instructions through a repeating fetch-decode-execute cycle. The control unit generates control signals, the arithmetic logic unit (ALU) performs arithmetic and logical operations, and registers provide fast internal storage.
| Stage | Main activity | Effect |
|---|---|---|
| Fetch | Retrieve the instruction addressed by the program counter | Load the instruction register and advance the program counter |
| Decode | Interpret the opcode and addressing information | Determine the operation and operand sources |
| Execute | Carry out the decoded operation | Update processor state, transfer data, or redirect execution |
The program counter (PC) holds the next instruction address, while the instruction register (IR) holds the current instruction. The memory address register (MAR) holds an address for a memory access, and the memory data register (MDR) holds data being transferred to or from memory.
Branches can change the program counter, enabling nonsequential execution. At an architecturally defined point, an enabled interrupt can cause the CPU to save execution state and transfer control to an interrupt handler. Saving and restoring state preserves the interrupted program's execution context.
Frequent memory accesses can limit performance. Modern processors may overlap instruction stages through pipelining, but the cycle remains useful for tracing machine-code execution.
Common Misconceptions: The PC holds an address, not the current instruction. Execution does not always continue sequentially. Pipelining overlaps stages rather than eliminating them.
🧠 Key Concepts
- Control unit
- Arithmetic logic unit
- Program counter
- Instruction register
- Memory transfer registers
- Fetch-decode-execute cycle
- Interrupt handling
- Instruction pipelining
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The Central Processing Unit and the Fetch-Decode-Execute Cycle
📘 Overview The central processing unit executes machine-code instructions through a repeating fetch-decode-execute cycle. Registers hold immediate working state, while the control unit coordinates instruction processing and the arithmetic logic unit performs arithmetic and logical operations.
🧠 Key Idea The CPU repeatedly fetches the instruction identified by the program counter, decodes its operation, and executes it. Execution changes processor state and may redirect which instruction is fetched next.
⚔️ Core Details: - CPU components: The control unit generates control signals; the arithmetic logic unit performs arithmetic and logic; registers provide fast internal storage. - Register roles: The program counter holds the next instruction address; the instruction register holds the current instruction; the memory address and memory data registers support memory transfers. - Fetch: The CPU retrieves the instruction at the program counter through the memory hierarchy into the instruction register, advancing the program counter to the next sequential instruction. - Decode: The control unit interprets the opcode and addressing information to determine the required operation and operand sources. - Execute: The CPU performs the decoded operation, such as calculating a result, transferring data, or changing the program counter through a branch. - Interrupt handling: At an architecturally defined point, an enabled interrupt can cause the CPU to save execution state and transfer control to an interrupt handler.
🎯 Why It Matters: - Tracking the program counter explains sequential execution, conditional branches, loops, and function calls. - Distinguishing registers from main memory helps explain why frequent memory access can limit program performance. - The cycle provides a conceptual model for tracing machine code, even when modern processors overlap instruction stages through pipelining. - Saving and restoring processor state allows interrupt handlers to run without losing the interrupted program's execution context.
🧠 Quick Recall: - PC - Program counter; holds the address of the next instruction to fetch. - IR - Instruction register; holds the instruction currently being decoded or executed. - MAR and MDR - Memory address register holds an access address; memory data register holds data being transferred to or from memory. - Opcode - The instruction field specifying the operation the CPU must perform. - Fetch-decode-execute - Retrieve an instruction, interpret its operation, and carry out that operation.
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